This invention relates generally to digital computers and more particularly to microprogram controlled digital computers.
As is known in the art, many microprogram controlled digital computers generally include a macroprogram memory adapted to store a repertoire of macroninstructions, a microinstruction memory adapted to store sets of microinstructions, each one of the stored macroinstructions corresponding to a set of the stored microinstructions and a data flow unit including an arithmetic unit and registers to process data in accordance with the execution of selected macronistructions. The execution of a selected macroinstruction is accomplished by the execution of each one of the microinstructions in the corresponding set thereof. In the execution of each microinstruction control signals are produced and fed to the data flow unit to control the flow of data in such unit in accordance with such microinstruction. Each one of the microinstructions includes a data flow control field for controlling the flow of such data through the arithmetic unit and the registers, while also controlling the function the arithmetic unit is to perform on such data. In addition to such data flow control field, each one of such microinstructions includes a microinstruction memory address control field for selecting the address of the next microinstruction to be executed.
In a known microprogram controlled digital computer (as for example the digital computer described in U.S. Pat. No. 3,215,987, inventor J. Terzian, issued Nov. 2, 1965, and the digital computer described in copending patent application Serial No. 570,114, filed Apr. 21, 1975, entitled "Digital Processor," inventor John Terzian.) the microinstruction memory address control field selects either: (a) the address of the next sequential microinstruction in the set being executed; (b) an address designated in a JUMP field included in the microinstruction being executed (such as, for example, the address of the first microinstruction in a fetch microprogram stored in the microinstruction memory and used as a subroutine to obtain the next macroinstruction, the address of the first microinstruction in the fetch microprogram being designated by the JUMP field of the last microinstruction in the set being executed); (c) the operation code field of a fetched macroinstruction, such operation code field providing the address of the first microinstruction in the set thereof corresponding to such fetched macroinstruction; or (d) a fixed, hard-wired address, generally selected when a program interrupt signal is generated in the digital computer.
While such digital computer has been found adequate in many applications, the described microinstruction memory addressing control arrangement is limited in the degree of addressing versatility required in other applications. For example, in order to simplify the microprogramming of the digital computer it is sometimes desirable to select one of two possible microinstruction memory addresses, such address being selected in accordance with the existence or nonexistence of a selected condition (as, for example, whether the contents of a particular register are positive or not). In one known digital computer two JUMP fields are included in each one of the microinstructions, one of such two fields being selected as the address of the next microinstruction in accordance with the existence or nonexistence of the selected condition thereby requiring additional microinstruction word length and hence significantly increasing the size of the microinstruction memory. Further, in programming a digital computer of the type herein described, it is sometimes desirable to use in the execution of a set of microinstructions, a second set of microinstructions corresponding to a different macroinstruction as a subroutine. However, in the microinstruction memory address control arrangement described above, because the last microinstruction in each set thereof generally calls for the fetch microprogram which in turn calls for a macroinstruction from the macroinstruction memory, it is necessary to go through the macroinstruction memory in order to call for the desired subroutine, thereby increasing the execution time of the microinstruction set under execution.